Turning to FIG. 1, a conventional, synchronous ADC 100 can be seen. In operation, a analog signal AIN is filtered by and/or amplified by filter/driver 102 (which is typically an anti-aliasing filter) and provided to a sample-and-hold (S/H) circuit 104. The S/H circuit 104 is then able to periodically (usually at equidistant sampling instants as shown in FIG. 2) sample the analog signal AIN based on a signal from timing circuit 110. Conversion circuit 106 (which may be a type of quantizer) is then able to convert the sampled analog signal AIN to a digital representation having quantization levels (i.e., as shown in FIG. 2) using a clocking or timing signal from timing circuit 110. Output circuit 108 (which may include a digital correction circuit like an averager) generates the final digital signal DOUT.
ADC 100 can also be modified to be “level-crossing” ADC 150, as shown in FIG. 3. Here, the S/H circuit 104 and conversion circuit 106 are, respectively, replaced with a comparison circuit 154 (which may include comparators) and conversion circuit 156. For this ADC 150, it determines the time at which the analog signal AIN becomes greater than (or less than) the known, quantized levels (as shown in FIG. 4). Based on these times, the digital signal DOUT can be generated.
There are, however, some drawbacks to each of the ADCs 100 and 150. One drawback is that power consumption from the timing circuit 110 can be high because each ADC 100 and 150 may employ a large number of devices (i.e., comparators) or oversample at very high speeds to achieve a desired resolution. Therefore, there is a need for an improved ADC.
Some examples of conventional circuits are: U.S. Pat. No. 6,404,372; U.S. Pat. No. 6,850,180; U.S. Pat. No. 7,466,258; and Grimaldi et al., “A 10-bit 5 kHz level crossing ADC,” 2011 20th European Conf. on Circuit Theory and Design (ECCTD), pp. 564-567.